Schematic design with VHDL blocks. Contains an FSM, Ram, counter and various other blocks. The complete circuit is a RAM memory tester. The RAM is written to, and read from, every address using the two values 0xAA and 0x55. After all addresses have been tested, the green LED lights. If an error occurs the red LED lights.
Uses behavioural style descriptions of a RAM, FSM, Counter etc. This design shows the power of the VHDL language to model a number of digital system elements using Logicworks. The RESBAR input is active low and performs a system reset, the RAM test is initiated by setting Start switch to logic-1 momentarily.
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