Tutorial - Structural Simulation

This section of the tutorial will provide you with a closer look at the integrated digital simulator in LogicWorks, including the following topics:
Logic States
Logic State

LogicWorks uses a total of 13 different logic values for signals in order to handle different drive levels and unknown situations. The probe will display an X for any of the  possible "Don't Know" states. In this case, the X results from the fact that the device input is unconnected.
Binary switch as input to buffer
The Z value indicates a high-impedance or undriven line. Multiple open collector or three-state devices can drive a line to simulate bus or wired-AND logic.

Circuits with Feedback
Circuit with Feedback
Using the Signal Probe
Signal Probe
Using Probe
It will show the current value of the signal as the simulation progresses.

You can also use this tool to enter new signal values by typing 0 or 1 on the keyboard while the left mouse button is pressed. Stuck-at, unknown, and high-impedance levels can also be inserted.

Time Values

LogicWorks uses integers to represent simulated time values.  Most devices included with LogicWorks default to a delay of 1 ns (nano second, or 10-9 seconds).

LogicWorks uses an event-driven simulator, meaning that device values are recalculated only when an input change occurs. Thus, the speed at which the simulation occurs does not depend on delay or other time values in the circuit.

Primitive Devices
Simulation Params for NOT device

The inverter is classified as a primitive device, since its simulation function is built into the program. Primitive devices have a single time value that defines the delay from any input pin to any output pin for any transition.  More complex models can be implemented by using pin delays or by building subcircuit devices out of the existing primitives.
Power and Ground Signals
Power and Ground
Subcircuit Devices
Signal naming automatic

Notice that the traces D0 to D3 in the Timing window will show unknown values, because the counter has never been cleared into a known state.
Delay cannot be set

The 161 counter is a subcircuit device, meaning that its logic function is implemented using a combination of LogicWorks primitive devices. Because of this, the overall delay for the device cannot be adjusted by simply changing one parameter. Two methods are available for modifying delays in subcircuit devices and are discussed in the upcoming sections.
Internals of 161
Notice how you can use the Signal Probe tool, the Parameters command, and all the drawing tools to view and modify this internal circuit. If you modify this circuit, all devices of the same type in this design will be equally affected.

Pin  Delays
Pin Delays
LogicWorks allows you to set a delay on an individual pin on a primitive or subcircuit device. The logical effect is the same as if you had inserted a buffer device with the specified delay in series with the pin. Pins always have a default delay of Zero.
Set Pin Delay

Notice the effect this step has on the D0 trace in the Timing window.

Pin delays can be used to customize  path delays in subcircuit devices without opening and modifying their internal delays. Setting pin delays on a subcircuit device affects only the single device modified., whereas changing internal delays of primitive devices will affect all copies of the same type of device.

Moving Timing Traces

Moving Timing Traces

You can reposition any group of traces for ease in making timing comparisons. Any number of traces can be moved at once by holding the SHIFT key while clicking on the trace names.

Group Timing Traces
  • Click on the name D0 in the Timing window. Hold the SHIFT key down while you click on the names D1, D2, and D3 so that they are all selected.
  • Click the right mouse button on any of the four selected names.
  • In the pop-up menu, select the Group command.
You will now see that the four traces D0 to D3 collapse into a single grouped trace showing their combined value in hexadecimal.

Grouping Timing Traces
The same pop-up menu can be used to ungroup the signals again or to set the signal order used to create the hexadecimal value.

Note that the grouped trace has double vertical bars on some values. This is due to the delay we inserted in the QA output pin. If you set the pin delay back to zero, the double bars will revert back to single bars.

NOTE: The hexadecimal value of a grouped signal will be displayed only if there is sufficient space between the signal changes to display the text. You can use the zoom In and Zoom Out buttons (Zoom in and Zoom out buttons) to change the scale factor in order to see the values.

Using the Trigger

The trigger mechanism allows you to detect various timing and signal-state conditions.
Using the Trigger
You will now see that a reference line is drawn on the Timing window each time the CLK signal changes to a 1 state. You can also enter ranges of signal names(e.g. D7..0) and corresponding hexadecimal values (e.g. 7A) into these boxes in order to match more complex  events.

This completes the tutorial section on  structural simulation.

The next tutorial is Using VHDL in LogicWorks.