Tutorial - Using VHDL in LogicWorks

In this tutorial section, we'll look at how you can use the VHDL Language to create design descriptions and simulation models. LogicWorks allows you to create designs containing a mix of structural components (that is, schematic diagrams) and VHDL. The topics in this tutorial will get you started in creating each of these types of simulations and tying them together.

Creating a Simple VHDL Simulation

In this section, we create a simple, self contained VHDL simulation from scratch.

Creating a New VHDL Model
The Model Wizard allows you to crate either an independent, top  level design file or a component that can be used inside other designs. Any model can be created using either VHDL or a schematic circuit diagram..

The first panel of the Model Wizard looks like this:

Model Wizard
With these selections, we are essentially creating a new, independent circuit. That is, it will not at this stage be used as a description of a component used in another design.
The next pane allows you to choose which type of model you wish to create. In this case, we're going to use VHDL to create a simple AND gate with one inverted input that would look like this in an equivalent logic diagram.
AND Gate
Note:  Since this name will be used in the VHDL source file, you cannot use a VHDL reserved keyword or anything containing invalid characters as a name. For example, AND would not be a valid name.
We now specify the "interface" to the model, that is, what its inputs and outputs will be. In this case, we wish to add two single-bit inputs and one single-bit output. To do this, we proceed as follows: The port list should look like this:
Model Wizard

IMPORTANT: The settings in the Func column must appear as shown above!
You should now see a new document window open containing text like this:

library IEEE;
use IEEE.std_logic_1164.all;

entity AND1INV is

            POS: in         std_logic;
            NEG: in       std_logic;
            OUT1: out    std_logic;

end AND1INV;

architecture arch1 of AND1INV is


--Your VHDL code defining the model goes here

end arch1;

We now have a complete VHDL description of  a component having the desired inputs and outputs, except that no code has been added to describe the actual behaviour of the device. Before we proceed, we must verify that this is a correct VHDL file.

You will notice that a new panel appears at the bottom of the screen with the compilation results. You should receive a warning that output OUT1 has not been assigned.
            OUT1<=POS AND NOT NEG AFTER 1NS;

Running the Simulation
You will now see the VHDL text document turn gray to indicate that it cannot be edited while the simulation is running. Now we need a method of feeding inputs into our design and checking the outputs.
Note:  If the I/O Panel has already been used, you might need to click the I/O Panel tab in the Results Panel in order to bring it to the top.
IO Panel Default HTML

The I/O Panel is actually a special kind of Web page that can be programmed to display simulation results in many different ways. This default display show the top-level signals in the design being simulated.
pos neg OUT1
0 0 0
0 1 0
1 0 1
1 1 0

Displaying Timing Results

The I/O Panel is a quick way of viewing circuit inputs and outputs, but gives you no information about the relative timing of signal changes. To view the signals over time, we will use the Timing window.
Since the timing diagram was actually collecting results while you were using the I/O Panel, it will display the changes that have occurred up to now:

VHDL Timing Window
Normally, results windows all share the same panel at the bottom of the screen. If you wish to view the Timing and I/O Panel tab, and select the Float Current Tab command:
I_O Panel drop down menu
This command places the I/O Panel in a separate, floating window so that you can view both at the same time. You could also have done this to the  Timing tab, if desired.
Note that there is a 1-ns delay between input changes and the corresponding output change. This delay is due to the AFTER 1 NS specification in the VHDL model.

Creating a VHDL Model for a Device Symbol

We'll now look at how we can use VHDL to describe the operation of  a device that is going to be used in a  LogicWorks circuit diagram. We'll also take the opportunity to use vectors, or multibit signals.
Model Wizard dialog 2
Desired Model Type

Counter Dialog
The next panel allows you to specify where the pins will appear on the schematic symbol. By default, inputs will be placed on the left and outputs on the right, which should make sense for most applications. The panel appears as follows:
Pin Location Dialog
The last panel allows you to choose the library into which you want to save the new symbol.
Note: We do not recommend saving your own components into the libraries supplied with LogicWorks. Future upgrades to the software might replace those libraries, and you could lose your work.
The Model Wizard has now created a VHDL model file that describes all the inputs and outputs, but has no actual behaviour. It has also created a device symbol with entries linking it to the file. We now have two steps left: first to fill in the actual behavioural part of the VHDL model, and then to build a test circuit to make sure it works.
Count 8 Device
    use IEEE_numeric_std.all;
This line is needed because we will be using some arithmetic data types and operations that are defined in this package.
        clk_proc: process(CLK)
            variable COUNT: unsigned(7 downto 0):="00000000";
            if CLK'EVENT AND CLK ='1' then
                if LOAD ='1' then
                else COUNT:=COUNT+1;
            DOUT<=COUNT after 500ps;
        end process clk_proc;

NOTE: Take care when entering the fourth line in the preceding code. The item CLK'EVENT consists of the name CLK followed by an apostrophe (single quote) followed by the word EVENT. For more information on this VHDL attribute, consult a VHDL manual.
Although we could use the I/O Panel as we did in the previous tutorial, we'll take a different approach this time and add circuitry to the diagram in order to test the new device.
Count8 with Exteded DOUT

Breakout dialog for COUNT8
Beakout on DOUT of Count 8
Count8 with Hex Display on DOUT
DIN on COUNT8 with Bus
Count8 with DIN and DOUT
Here is our final circuit:
Final COUNT8
You should now see the signal value displays change and the time indicator in the toolbar start to advance. Time is advancing because of the Clock device we placed in the circuit. This device generates a continuous sequence of 0-to-1 value changes at its output, regardless of  what else is happening in the circuit.

Using a LogicWorks Symbol in a VHDL Design

In this tutorial, we will create a design by using VHDL to create the top-level description and having it refer to LogicWorks symbols as building blocks. This is the reverse of the situation described in the previous tutorial.

Important: The VHDL language has more severe restrictions on names than the general LogicWorks program. In order for a symbol to be usable as a device model within a VHDL description, the name of the library itself, the name of the symbol and the names of all pins on the symbol must meet VHDL naming requirements. In general, this means that names cannot contain any spaces or special characters. Most of the libraries provided with LogicWorks do not meet these requirements, so you must either use the specific libraries provided for this purpose or create your own versions of libraries that have appropriate names.
We now specify the "interface" to the model, that is, what its inputs and outputs will be. In this case, we wish to add three single-bit inputs and two single-bit outputs. To do this, we proceed as follows:
The port list should now look like this:

Port List
You should now see a new  document window open containing text like this:

library IEEE;
use IEEE.std_logic_1164.all;

entity FULL_ADDER is

        c_in    : in    std_logic;
        a        : in    std_logic;
        b        : in    std_logic;
        sum        : out    std_logic;
        c_out    : out    std_logic


architecture arch1 of FULL_ADDER is


  -- Your VHDL code defining the model goes here

end arch1;

To make this code into a complete description, we will add component instantiation statements that refer to LogicWorks gate symbols stored in libraries.
        library Libs;
        use Libs .VHDLPrims.all;

These statements tell VHDL where to find the components to which we will be referring. The name, in this case VHDLPrims, must refer to a library that is already open in the LogicWorks parts palette.
        signal s1, s2, s3 : std_logic;

This line creates some intermediate signals that will be part of  our model.
            G1 : xor_3 port map(INA=>c_in, INB=>a, INC=>b, Y=>sum);
            G2 :and_2  port map(INA=>c_in, INB=>a, Y=>s1);
            G3 :and_2  port map(INA=>a, INB=>b, Y=>s2);
            G4 :and_2  port map(INA=>c_in, INB=>b, Y=>s3);
            G5 :or_3  port map(INA=>s1, INB=>s2, INC=>s3,  Y=>c_out);

The xor_3, and_2, and or_3 components are all items that will be fetched from the LogicWorks library VHDLPrims. The component names and pin names must exactly match those defined on the symbol.
a b c_in sum c_out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

NOTE:  The delay values used by the LogicWorks symbols are determined by settings that were supplied when the symbols were created. There is no way of changing the delays in the symbols themselves from the VHDL file., although you could apply additional delays to the signals.

The next tutorial is Createing a Device Symbol.